Phase-locked loop architecture for enhanced voltage-controlled oscillator phase-noise suppression

In traditional phase-locked loop (PLL) designs, the loop bandwidth is limited to ~1/10^th of the frequency of the reference clock due to the discrete-time nature of the system. The loop bandwidth also sets the frequency above which no significant suppression of the phase noise of the oscillator in the PLL occurs. This paper describes a PLL architecture in which the output of an additional charge pump drives a feed-forward path that extends outside of the PLL's feedback loop. This path drives a phase interpolator, allowing for phase-error correction to occur beyond the bandwidth of the PLL. The proposed architecture is investigated through linear analysis. Measurements of a test chip designed in TSMC 90 nm technology show that the proposed architecture is effective in reducing PLL phase noise.