FPGA based design and implementation of modified Viterbi decoder for a Wi-Fi receiver

Viterbi Decoders are employed in digital wireless communication systems to decode the convolution codes which are the forward error correcting codes. Although widely-used, the most popular communications decoding algorithm, the Viterbi Algorithm (VA), requires an exponential increase in hardware complexity to achieve greater decode accuracy. When the applications based with wireless technology has been developed tremendously with the world. The constraint length associated with the input bits are large, hence it needs to implement the larger constraint length with lesser hardware and lesser computations for decode the original data. When the decoding process uses the Modified Viterbi Algorithm (MVA) computations 50% reduced and reduction in the hardware utilization, which follows the maximum-likelihood path. It shows plan ahead associated with the modified Viterbi decoder implementation using Xilinx tool in verilog design. An implementation on Field Programmable Gate Arrays (FPGA) provides user flexibility to a programmable solutions and lowering the cost.