Code-density calibration of Nyquist-rate analog-to-digital converters

An analog-to-digital converter (ADC) calibration algorithm based on measuring and correcting the code-density histogram of the converter under calibration is presented. The algorithm constructs a histogram of the ADC response to a linear ramp and stores the calculated correction coefficients in a lookup table. By leveraging circuit density improvements in deep submicron CMOS technology, the algorithm is able to provide substantive improvements to ADC static linearity performance at low silicon cost. The algorithm is applied to a 12-stage prototype Pipelined ADC implemented in 65 nm CMOS technology and is able to improve measured integral nonlinearity from −5.31/1.02 least significant bit (LSB) to −0.24/0.31 LSB at a 10-bit level, an improvement of over three effective bits.