Progress of FD-SOI technology for monolithic pixel detectors

We have been developing the 0.2 μm fully-depleted Silicon On Insulator (SOl) CMOS technology for monolithic pixel detectors. In order to improve the sensor's sensitivity, 8 inch FZ wafer is introduced for handle substrate in SO! wafer. Stitching technology is also developed to get large detector chip area. Furthermore, nested well structure for the p-n junction and double-SOI structure are investigating for reducing the radiation damage and crosstalk between electrical circuitry in top silicon layer and sensors at substrate. In this document, recent progress of process technology for pixel detector is described.