FPGA implementation of 16-point radix-4 complex FFT core using NEDA

NEDA is one of the techniques to implement many digital signal processing systems that require multiply and accumulate units. FFT is one of the most employed blocks in many communication and signal processing systems. This paper proposes FPGA implementation of a 16 point radix-4 complex FFT core using NEDA. The proposed design has improvement in terms of hardware utilization compared to traditional methods. The design has been implemented on a range of FPGAs to compare the performance. The proposed design has a power consumption of 728.89 mW on XC2VP100-6FF1704 FPGA at 50 MHz. The maximum frequency achieved is 114.27 MHz on XC5VLX330-2FF1760 FPGA at a cost of higher power and the maximum throughput observed is 1828.32 Mbit/s and minimum slice delay product observed is 9.18. The design is also implemented using synopsys DC synthesis for both 65 nm and 180 nm technology libraries.