A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier

This paper presents a 3-GS/s 5-bit interpolated Flash ADC with a wideband input buffer amplifier. Small input capacitance of the ADC is necessary to achieve high signal bandwidth with low power consumption of the input buffer. The design challenge is a reduction of power consumption of the interpolated Flash ADC and the input buffer simultaneously. To solve this, the interpolation technique using reference voltages is proposed to reduce the input capacitance and interpolated stages simultaneously. The prototype is fabricated in a 65-nm CMOS technology. The measured results show that the cutoff frequency is 1.6 GHz, the peak spurious-free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR) are 33.1 dB and 23.1 dB at nyquist frequency, respectively. The power consumption including the input buffer is 39.4 mW, and the Figure of Merit (FoM) of 0.58 pJ/conversion-step is achieved.