An on-chip dynamic supply current monitor for testing of digital circuits

The paper deals with the dynamic supply current testing (I_DDT) of SRAM cells and arrays. An I_DDT current sensor and sensing method are presented and explained. The effects of leakage current and static current consumption on the monitoring technique and efficiency are also discussed. The efficiency of the proposed test in unveiling weak open defects is demonstrated through simulations carried out on a 64-bit SRAM array designed in a 90 nm CMOS technology.