New multilevel inverter topology with reduced number of switches using advanced modulation strategies

This paper presents a new class of three phase seven level inverter based on a multilevel DC link (MLDCL) and a bridge inverter to reduce the number of switches. There are 3 types of multilevel inverters named as diode clamped multilevel inverter, flying capacitor multilevel inverter and cascaded multilevel inverter. Compared to diode clamped & flying capacitor type multilevel inverters cascaded H-bridge multilevel inverter requires least no. of components to achieve same no of voltage levels and optimized circuit layout is possible because each level have same structure and there is no extra clamping diodes or capacitors. However as the number of voltage levels m grows the number of active switches increases according to 2×(m-1) for the cascaded H-bridge multilevel inverters. Compared with the existing type of cascaded H-bridge multilevel inverter, the proposed MLDCL inverters can significantly reduce the switch count as well as the number of gate drivers as the number of voltage levels increases. For a given number of voltage levels, the required number of active switches is 2 (m-1) for the existing multilevel inverters, but it is m+3 for the MLDCL inverters. The output of proposed MLDCL is synthesized as the staircase wave, whose characteristics are nearer to a desired sinusoidal output. The proposed MLDCL inverter topologies can have enhanced performance by implementing the pulse width modulation (PWM) techniques. This paper also presents the most relevant control and modulation methods by a new reference/carrier based PWM scheme for MLDCL inverter and comparing the performance of the proposed scheme with that of the existing cascaded H-bridge multilevel inverter. Finally, the simulation results are included to verify the effectiveness of the both topologies in multilevel inverter configuration and validate the proposed theory. A hardware set up was developed for a singlephase 7-level D.C. Link inverter topology using constant pulses.