Systolic FIR Filter Design with Various Parallel Prefix Adders in FPGA: Performance Analysis

FIR filters are the most common DSP function implemented in FPGAs. Systolic designs represent an attractive architectural paradigm for efficient VLSI and FPGA implementation of computation-intensive digital signal processing applications supported by the features like simplicity, regularity, and modularity of structure. The core elements in any systolic FIR filters are adders, multipliers and delay elements. Adders are one of the critical elements in VLSI chips, therefore careful optimization is required. This paper presents the implementation of systolic FIR filter architecture in FPGA. The work focuses the design of new parallel prefix adder (PPA) with minimal depth algorithm and its performance is compared with the existing architectures in terms of delay and area. The necessities of the parallel prefix adder are primarily fast and secondarily efficient in terms of power consumption and chip area. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size. The proposed adder and the existing PPA is incorporated in the systolic FIR filter and its performances are observed. The module functionality are described using Verilog HDL and performance issues like slice utilized, simulation time, input arrival time, frequency are analyzed at 90 nm process technology using XILINX ISE12.1 SPARTAN3E. The simulation results reveal better delay and slice utilization for proposed PPA as compare to the existing adder schemes.