A 6.25Gb/s adaptive analog equalizer in 0.18μm CMOS technology for high-speed SerDes

This paper presents a 6.25Gb/s adaptive analog equalizer in 0.18μm CMOS technology. Using a high-frequency boosting filter and a unity gain filter combined with a feedback control circuit, this analog equalizer can minimize the ISI adaptively for a variety of channels. The high-frequency boosting filter is based on the RC-degeneration and inductive peaking technique is used to increase the bandwidth. As a result, a peaking gain of nearly 20dB can be obtained around 6.25GHz. Additional, a method of zero-pole cancellation is also employed for unity gain filter to improve the bandwidth up to 9GHz and save power consumption as well. This equalizer has been tapped out and has a total area of 0.55×0.76μm² including I/O pads, with a power consumption of 45mW under 1.8V power supply. Post simulation results show that this circuit can eliminate the ISI significantly and the horizontal eye opening for 24-inch trace can be up to 0.75UI at 6.25Gb/s.