Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs

The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-k/metal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500–900 °C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1–0.3 nm and interface state density at flatband below 2·10¹¹ cm⁻²eV⁻¹. The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 °C.