A 2.3-mW, 5-Gb/s decision-feedback equalizing receiver front-end with static-power-free signal summation and CDR-based precursor ISI reduction

This paper demonstrates a low-power decision feedback equalization (DFE) receiver with 0.46-mW/Gbps efficiency that can compensate up to −15-dB of channel loss while operating at 5-Gb/s. The key is the use of a clocked comparator design that can also perform the signal summations required for 1-tap direct-feedback DFE, additional DFE with an infinite impulse response (IIR) filter, and offset compensation, all without dissipating any static current. As a result, the power-hungry, high-bandwidth stages used in the prior backplane DFE receivers such as the continuous-time linear equalizer (CTLE), current-mode summing circuits, and fast selection logic for loop-unrolling DFE are all removed in this design. The pre-cursor ISIs are mitigated with passive inductive peaking at the termination loads and CDR timing adjustment, instead of a CTLE. A prototype DFE receiver fabricated in a 65nm LP CMOS demonstrates the measured eye opening of 112-mVpp and 0.66-UIpp while operating at 5-Gb/s with a −15-dB-loss channel.