Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at
V
_DS
=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <; 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very low
V
_DD
=0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at
V
_DD
=1.0 V.