A novel delay minimization technique for low leakagewide fan-in domino logic gates

With the scaling of technology the magnitude of leakage current has become a major cause of concern as it reduces the robustness of the circuit and leads to wastage of power. Most of the methods of leakage reduction lead to an increase in the delay of the circuit. In this paper a delay minimization block is proposed. This block is incorporated in a domino gate which has high threshold transistors for leakage reduction. The delay of high threshold domino gates has been reduced by using this mechanism. This facilitates the placement of high threshold domino gates in the critical or near critical paths of a design. Delay reduction of about 10% is achieved without any penalty on power delay productwhen wide fan-in domino gate has leakage as well as delay reduction features as compared to wide fan-in domino gates with only leakage reduction mechanisms. Simulations at 500MHz in 90nm show that leakage has reduced by 50% in the proposed design as compared to the conventional wide fan-in domino gate.