Modeling and characterization of the thermal performance of advanced packaging materials in the flip-chip BGA and QFN packages

This work describes an investigation into the performance of packaging materials, developed with a specific aim in improving thermal performance, such as silver-sintered materials that perform both die-attach and thermal-interface-material (TIM) duties. The test vehicles under study consist of a flip-chip BGA package (die size: 10.2×10.2×0.3mm in a package of 21×21×1.5mm) and a molded QFN package (thin die size: 5×5×0.070mm in a package of 8×8×0.7mm) Parametric thermal modeling using Finite-Volume-Method Simulation thermal modeling software covers the effect on package thermal resistance (junction-to-case) due to package geometry parameters, interface thickness (bond-line thickness), void coverage, thermal conductivity and contact resistance. In addition to steady-state thermal resistance, transient analysis of the QFN structure under a high frequency operational power profile is also investigated. Finally, experimental thermal characterization of the device for thermal resistance (junction-to-case) is also conducted under time-zero conditions and post-reliability tests (such as Moisture Sensitivity (JESD22-A113-D MSL3 and MSL1), Temperature Cycling (JESD22-A104-G TC-condition B or C), High Temperature Storage (HTS, +150°C and 1000 hours) and Unbiased Highly-Accelerated Stress Test (HAST)).