Modeling of pattern-dependent on-chip interconnect geometry variation for deep-submicron process and design technology

A set of closed-form equations with calibrations based on test chip characterization is used to describe systematic geometry variation in submicron multilevel interconnect. Two predominant modes of systematic interconnect variation, dielectric thickness variation induced by pattern-dependency of Chemical-Mechanical Polishing (CMP) and metal width variation from lithography bias, the loading effect and the proximity effect, are modeled by the equations. In this paper we detail our process variation model and its calibration methodology. The model has extensive applications both in process control improvement and in the design automation of today's deep submicron design technology. As an example, this paper demonstrates that the model sufficiently improves the efficiency of CMP process control, the accuracy of interconnect capacitance extraction, and 3-/spl sigma/ estimation of interconnect capacitance and resistance variation.