FIFO Design for IEEE 802.3 Standard 10GBase-X PCS and XGXS Sublayers

This paper analyses the FIFO design for the receiver of 10GBase-X PCS sublayers specified by IEEE 802.3 CSMA/CD Standards. The proposed FIFO design will save the gate count, power and the silicon area in ASIC design considerably.

I. Introduction

Local Area Networks (LAN) are based on the Ethernet technology and the commonly used 10 Gigabit Ethernet systems are adopting the IEEE 802.3 standards [1]–[4]. The 10Gbase-CX4 and 10Gbase-LX4 designs defined by the IEEE 802.3 standards have 4 serial lanes at the physical layer and therefore the lane synchronization has to be carried out by the receiver side [5], Clause 48. The synchronization state diagram for the PCS receiver is given in [5], FIG 48.7. Each lane requires one FIFO bank to store the received data at the receiver. Since there are 4 serial lanes, 4 FIFO banks have to be employed at the receiver. The recovered clock from the serial lane data is used to store the received data in the FIFOs. It means the write pointer is controlled by the recovered clock. The local clock is used to read the stored data and hence controlling the read pointer. The implementation of this FIFO bank is required at the receiver side of the PCS and XGXS sublayers. The transmitter and the receiver functional block diagram are shown for the 10Gbase-X PCS layer in [5], Clause 48.1.6.