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FIFO Design for IEEE 802.3 Standard 10GBase-X PCS and XGXS Sublayers | IEEE Conference Publication | IEEE Xplore

FIFO Design for IEEE 802.3 Standard 10GBase-X PCS and XGXS Sublayers


Abstract:

This paper analyses the FIFO design for the receiver of 10GBase-X PCS sublayers specified by IEEE 802.3 CSMA/CD Standards. The proposed FIFO design will save the gate cou...Show More

Abstract:

This paper analyses the FIFO design for the receiver of 10GBase-X PCS sublayers specified by IEEE 802.3 CSMA/CD Standards. The proposed FIFO design will save the gate count, power and the silicon area in ASIC design considerably.
Date of Conference: 29-31 January 2013
Date Added to IEEE Xplore: 15 April 2013
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ISSN Information:

Conference Location: Bangkok, Thailand

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