GALS architecture of H.264 video encoding system on DN-DualV6-PCIe-4 FPGA platform

To manage the increasing complexity of modern digital systems, Globally-Asynchronous Locally-Synchronous (GALS) is considered a promising solution, which is now widely adopted in large FPGA designs. The GALS methodology can effectively maximize the performance-power-ratio of the electronic system along with great reuse capability. With multiple clock domains in a GALS system, the accuracy with data transmission between different clock domains counts for a lot. In this paper, a GALS architecture of H.264 video encoding system is implemented on the DN-DualV6-PCIe-4 FPGA platform from the Dini Group. The data rate conversion module among different clock domains is designed with a stream controller and asynchronous FIFOs, in which gray code is applied to avoid metastability. The experiment results show the correctness and effectiveness of the proposed implementation. Furthermore, the proposed GALS scheme can be applied as a configurable architecture for more complicated applications.