Thermal measurement method for multi-chip packages

Semiconductor industry is constantly improving. Package technology are getting more and more complicated with the industry trying to squeeze passive components and more dies in a package to increase functionality of products. [1] Emerging names for these packages are for example multi-chip packages, package on package, package in package, modules and etc. [2] With the increasing number of die per package, semiconductor industry is facing thermal challenges with increase of power which generates more heat in package. [3] Question is how do we characterize and perform thermal measurement to decide if those packages will meet thermal performance? Conventional methods are available for single chip packages. This paper will describe thermal measurement approach of multi-chip packages using linear super-position method. 16 lead SOIC package mounted on a 2 layer standard JEDEC thermal test board is employed as test vehicle for this study under still air environment. Its accuracy will be validated through finite element modeling using ANSYS software simulation tools. Wiring connection method implemented in this study will be demonstrated as well.