Optimization of VLSI architectures for DTW

In data mining and time series recognition applications Dynamic Time Warping (DTW) is a very popular method. It can produce accurate results provided its originality is preserved. But its lethargic nature has been inspiring development of its hardware based acceleration methods. In this paper, four novel VLSI architectures for performing DTW are proposed and compared. The comparison reflects achievement of significant conclusions specifically for performance critical and memory constraint applications.