Does PMOS Vth shift wholly capture the degradation of CMOS inverter circuit under DC NBTI?

In this paper, an experimental investigation of negative bias temperature instability (NBTI) impact on CMOS inverter circuit is presented. The study focuses on the contribution of NBTI induced PMOS V_th shift on the degradation of the circuit DC features. This investigation was conducted in order to understand the origin of performance shifts due to NBTI at the circuit level and to properly predict the lifetime of the inverter circuit. The experimental setup was based on a measure/stress/measure procedure, where a series of negative gate voltages at different temperatures were applied via an automated test bench to the circuit under test. The results we obtained show, on one side, the CMOS inverter voltage transfer curve (VTC) shifts under NBTI stress to the left side, as predicted by the theory. This shift implies a shift of the critical logic voltages of the inverter. On the other side, the analysis of the logic threshold shift with respect to the inverter's PMOS threshold voltage shift shows clearly, and contrary to predicted by theory, that PMOS threshold voltage (V_th) shift does not wholly capture the degradation of the CMOS inverter logic threshold shift. In fact, this later is found to be affected by both PMOS and NMOS V_th shifts. Therefore, it cannot be unconditionally assumed that the effect of NBTI on CMOS circuits could be exclusively predicted by only shifting the PMOS Vth.