Process optimization for random threshold voltage variation reduction in nanoscale MOSFET by 3D simulation

Process optimization strategy to reduce random threshold voltage (Vt) variation for CMOS at 65 nm and beyond is presented. The impact of related process parameters such as halo/Vt implant species, energy and dosage on Vt mismatch are analyzed and compared by 3D TCAD simulation. It is revealed that the random dopant fluctuation (RDF) can be dramatically suppressed by carbon implant with sufficient dosage combines proper energy. Besides, Vt tuning and halo implants by indium is recommended because it is less susceptible to Vt variation than Bf2. All these results of process optimization can be well explained by the shift of impurity doping level near the surface.