A path-matching timing optimization in physical design for DDR port of a global switch chip

Nowadays, collective communication is becoming the bottleneck of the problem when processing large scale communication. The global network switching chip (D6000GSW) is the core component of Dawning 6000 network system, which realizes the high speed collective communication between the nodes in the computing system. The RX/TX ports of the chip are using DDR transferring mode, so it is important to meet the timing of the these ports. During the physical design stage, various placement and routing will affect the timing result of the DDR ports. The OCV effect will make timing even worse. So in the physical design, we need optimize the timing of these input/output paths. In this paper, a path-matching method which include a full flow from defining the timing constraint to engineering change order(ECO) is present to optimize this SSD timing. The main idea of this method is matching the clock path delay and the data path delay in the DDR port to be identical. Thus the respective timing phase of the input/output data and input/output clock will be good for next level chip. Here we also customize a new pad cell called “WYSSTL2C”. The new pad merges the IO pad and the DDR logic cells together in order to make the data path delay and clock path delay be equal. When the two path is well matched, it is good for the timing closure. Finally, the chip is taped out and passed the testing that prove the design flow is effective.