High voltage SJ-LDMOS with charge-balanced pillar and N− buffer layer

A novel SJ-LDMOS using charge-balanced pillar and N⁻ buffer layer (CBB) is proposed. The charge-balanced pillars which provide additional charges for compensating a surplus of p-type charges around the drain end insure the charge balance and eliminate the substrate assisted depletion effect. In addition, the N⁻ buffer layer under SJ region enables CBB SJ-LDMOS to use shallow pillars. Therefore the CBB SJ-LDMOS is compatible with CMOS technology. Simulation results indicate that the surface lateral electric field of the CBB SJ-LDMOS reaches 23.3V/μm, resulting in a breakdown voltage (BV) of 350V with 15μm drift length.