A compact implementation of masked AES S-box

A masking scheme of AES algorithm is analyzed, and the optimal masked S-box is implemented in this paper. By using the “tower field” representation, all nonlinear process of unmasked S-box is mapped to multiplication in GF(2), which is a single AND gate in circuits, and power consumption is hidden by using additive masked. In order to further reduce the hardware cost, a simplified masked AND gate is adopted and masks are reused safely. Both gate-level simulation and FPGA testing result have proved that our implementation provides good resistance against DPA attack.