Bist controller with efficient decoder and adder for high speed embedded memory applications

With rapid increase in the use of embedded applications, the complex designs need huge amounts of on chip memory. The most preferred choice for high speed testing is the BIST. In this paper a decoder-adder design using low power Gate Diffusion Input (GDI) technique is proposed. The dynamic component of power is reduced, as the source of PMOS is not permanently connected to V_dd. It also reduces the latency of the circuit. The outcomes are compared with traditional CMOS logic decoder-adder design. The results show a power saving of 88.03% for the adder and 99.19% for the decoder. The delay is found to be reduced at least by a factor of 2 for the proposed decoder-adder design.