Design flow of reconfigurable embedded system architecture using LUTs/PLAs

Hardware acceleration and optimization remarkably increases the performance of embedded systems built with reconfigurable computing devices. Reconfigurable computing perform with the help of Reconfigurable devices like FPGA which offer a technique for satisfying performance and flexibility simultaneously with the existing hardware resources for various computations. In this paper, hybrid architecture for reconfigurable embedded system (RES) is proposed which comprised of programmable logic arrays (PLAs) and Look up tables (LUTs) structures. Hybrid (LUTs/PLAs) structure for RES is recognised as Hybrid Reconfigurable Computing Architectures (HRCA). HRCA distributes the implemented digital circuit between LUT and PLA structures because some parts of digital circuit are well matched to implement through LUTs and some other parts are more benefited from product term like structure (PLAs). For several classes of high performance applications, HRCA offers significant savings in total computational delay and logic area comparison with a symmetrical FPGA which contain only LUTs. To address the performance of HRCA, a design flow concept is proposed and various design steps are defined and applied to perform experiments. Initially, results indicate that notable saving in computational delay and logic area of HRCA over symmetrical FPGA. Experiments are performed through MCNC benchmark circuit.