Performance analysis and simulation study of a Sandwiched Barrier Tunnel FET

The Sandwiched Barrier Tunnel FET is a promising device for low power applications. It shows a steep subthreshold slope and a CMOS compatible high ON-STATE current, (I_on). In this paper we present a simulation study to investigate the dependence of key device metrics on various structural parameters. We also present a simple model for the subthreshold current assuming an extreme retrograde doping profile. The assumption made, is justified through simulation results.