An algorithm facilitating fast BCD division on low end processors using Ancient Indian Vedic Mathematics Sutras

The last decade or two has witnessed a rapid evolution of the technological world with the introduction of fast processors loaded with higher amount of cache memories. Accordingly, the system architecture demanded better development to suit the rising demand for the technological advancements. Miniaturizations of components and VLSI integration have given rise to bulk advanced memory chips being grafted on even smaller amount of space thus giving access to higher amount of physical memory within exhaust limits of average applications. But the low end processors having limited memory still crave for fast applications, which are slowly going out of bounds for these devices due to the space and time complexity. The four elementary operations - addition, subtraction, multiplication and division form the basis for any type of application. Out of the four, the latter one, namely division, is a highly expensive and time consuming operation. This paper proposes a fast division algorithm based on Ancient Indian Vedic Mathematics Sutras for low end processors having limited memory. The novelty of the algorithm is that it requires a very small amount of memory for execution but performs the division mechanism much faster than the conventional division algorithms in literature, and is equally suitable for high end processors also. The algorithm has been tested on conventional mid range desktop processors and has furnished results with numbers having number of bits greater than 50 (15 digit numbers), the upper ceiling of computable numbers for conventional algorithms. It has been observed that the Vedic Division Algorithm can divide numbers having up to 38 digits (127 bits) in the present form, if modified it can divide even bigger numbers.