Thin glass substrates development and integration for through glass vias (TGV) with copper (Cu) interconnects

Silicon interposers have attracted a lot of interest for Three-Dimensional Stacked Integrated Circuit (3DS-IC) integration. Development of an advanced Si interposer derives from three essential technologies: front-side multi-level-metallization, through-substrate-vias and backside metallization. The approaches used for these technologies are greatly dependent on the application requirements, especially for the through silicon via (TSV) technology. Process development, optimization, and cost remain challenges to the industry. While silicon traditionally has been used in this application, glass has properties that make it a very intriguing material for through-substrate via applications. We note that “glass” describes a broad material set, with a wide range of properties driven by composition. Compositional changes allow tailoring of various properties, such as mechanical, thermal, electrical, optical characteristics, and even chemical durability. Compared to Si, one notable advantage of glass is the ability to alter the coefficient of thermal expansion (CTE), making glass a promising material for different applications in the 3DS-IC, because stack warpage due to CTE mismatch is a significant reliability concern. Another key advantage of glass interposer over Si interposer is that glass is an inherent insulator. This is useful for Cu interconnects, because no dielectric layer is required before the Cu plating/filling process to achieve low level leakage current. The elimination of this process step provides the benefits of reduced cost and complexity. Conventionally, a Si interposer has to be ground and polished in order to form the TSV. This step is cost prohibitive and time-consuming. On the other hand, due to the fusion-draw glass forming process used at Corning, ultra-thin glass can be provided in high volume as-formed (no polishing), with a pristine surface and tight tolerances (300 mm OD, thickness <; 0.10 mm (see Fig. 1), 30 μm warp and 1 μm total thickness variation (TTV)). Such a supply of as-formed ultra-thin glass wafers can compete very favorably in cost relative to polished or thinned glass or silicon wafers. Various technologies can be used to form through holes in glass. However, via size and pitch, wafer strength, and feasibility of mass production, are always challenges. At Corning we have made substantial progress in TGV processes, demonstrating high-quality through and blind holes in glass, with dimensions as small as 20 μm in diameter, and with glass as thin as 100 μm. Outstanding strength properties of TGV substrates have also been demonstrated. In brief, we have implemented through-substrate vias on glass with integrated Cu interconnects for 2.5D-IC and 3DS-IC application. Fusion-formed glass accompanied with new via formation processes provides advantages in cost and flexibility, along with excellent material attributes (CTE, electrical, strength, etc.). The significant advantages provided make a glass interposer a promising component for 3DS-IC technology.