Metrologies for characterization of flatness and thickness uniformity in temporarily bonded wafer stacks

In the past few decades, the semiconductor industry has grown very quickly and the technology has advanced as predicted by Moore's law. In order to improve the cost effectiveness of semiconductor processes, the device size has been reduced, but the wafer diameter continues to increase. Furthermore, in order to overcome the barrier of Moore's law, Three-Dimensional Stacked Integrated Circuits (3DS-IC) integration technology attracts more and more interests in the semiconductor industry. One of the key processes of 3DS-IC technology is the implementation of temporary bonding solution which gives the ability to handle and process thinned Si wafers. Flatness and thickness uniformity of a thin Si wafer is critical for product reliability and yield. As a result, not only total thickness variation (TTV) of the thin Si wafer but also TTV/flatness of the wafer stack matters.