Overview of recent advances in hardware implementation of mathematical morphology

This paper surveys the state of the art of mathematical morphology from a perspective of algorithmic advances of the low-level morphological operators dilation and erosion as well as implementation of these algorithms in the dedicated hardware, such as FPGAs. The existing architectures are categorized in three groups: neighborhood processors, partial-result reuse, and efficient algorithm implementation. The performance of recent proposals was compared on an ASF filter application.