An analysis of output ripples for PMOS charge pumps and design methodology

An analysis of output ripples for PMOS charge pumps is presented. Since the on-resistance of switching transistor plays an important role, the analytical model including this effect is derived and extensively verified by simulations using the 0.35 μm CMOS technology with errors within 7%. The measurement results also agree with the simulations. Based on the model, the guidelines to select the boosting capacitors, on-die output filtering capacitor and the optimized transistor sizes at the output stage are proposed. It would be helpful to design reduced-ripple PMOS charge pumps with good power efficiency and high boosted voltages.