A small die area and high linearity 10-bit capacitive three-level DAC

A 10-bit capacitive three-level digital-to-analog converter (TLDAC) is provided to reduce differential non-linearity (DNL) and integral non-linearity (INL) caused by capacitive mismatch. The simulation results of binary-weighted TLDAC show 50 % reduction in DNL and INL compared to conventional binary-weighted DAC. Furthermore an additional reference voltage source has been reduced due to the advantages of differential circuit. The proposed 10-bit differential TLDAC was implemented in 0.18 μm CMOS process and its total area is 0.081 mm².