A 16-channel 15 ps TDC implemented in a 65 nm FPGA

We present the implementation of a high-resolution Time-to-Digital Converter (TDC) targeting an Field Programmable Gate Array (FPGA) from Xilinx Virtex-5 family. The design of TDC is based on a counter and an interpolator method. Dedicated carry-in lines in CARRY4 block of Virtex-5 FPGA are utilized for time interpolation, which gives fine time measurements within a system clock period. Our test shows that the delay from CIN to COUT in CARRY4 block is as large as 104 ps. Thus we need to subdivide the delay of CARRY4 into finer taps for a higher resolution. Temperature, power voltage and process variations are common causes to the inhomogeneous delay cells. However, uneven delays need to be calibrated due to the dividing operation. Multiple strategies are applied to calibrate the non-uniformity of delay cell and to enhance the TDC resolution. Meanwhile, we also apply Place and Route (PAR) constraints to fit our TDC design. Finally, a total of 16 channels with the timing performance of about 15ps RMS, 30 ps Bin per channel are implemented in an FPGA.