Novel architecture of pipeline Radix 22 SDF FFT Based on digit-slicing technique

The prevalent need for very high speed digital signals processing in wireless communications has driven communications system to higher levels of performance. The objective of this paper is to propose a novel structure for efficient implementation of the Fast Fourier Transform (FFT) processor to meet the requirements of high speed wireless communication system standards. Based on the algorithm, architecture analysis, a design of pipeline Radix 2² SDF FFT processor based on the digit-slicing Multiplier-Less technique is proposed. Furthermore, this paper proposes an optimal constant multiplication arithmetic design to multiply a fixed point input by means of one of the several present twiddle factor constants. The proposed architecture was simulated using MATLAB software and the Field Programmable Gate Array (FPGA) Virtex 4 was targeted to synthesise the proposed architecture. The design was tested in real hardware of TLA5201 logic analyzer and the ISE synthesis report resulted in high speeds of 669.277 MHz with a total equivalent gate count of 14,854. This is a significant improvement over the Radix 2² DIF SDF FFT processor from which it can be concluded that the proposed pipeline Radix 2² DIF SDF FFT processor based on digit-slicing multiplier-less is capable of solving the problems that affect the capabilities of most high speed wireless communication systems in FFT and possesses huge potential for future research.