A multi-core FPGA-based SoC architecture with domain segregation

Nowadays, FPGAs are sufficiently large to host not only single soft-core CPUs but a whole Multi-Processor System-on-a-Chip (MPSoC). They follow the recent trend of chip-multiprocessing. Given the requirement for domain segregation in safety and security related applications, we propose an FPGA-based architecture that achieves segregation by secure bus bridges. According to the SoC-paradigm, we use a single shared memory controller to reduce external component count. We pay special attention to performance evaluation and avoidance of temporal conflicts. The architecture is evaluated by dedicated bus observers using simulation and hardware prototypes and is finally benchmarked by running multiple isolated off-the-shelf Linux systems.