High throughput Farrow re-samplers utilizing reduced complexity FIR filters

New VLSI high throughput parallel structures for arbitrary rate non integer ratio sample rate conversion are presented in the paper. High throughput Sample Rate Converters (SRC) find application in high data rate Software Defined Radio (SDR) where a large degree of flexibility is required to support varied sample rates. Parallel Signal Processing implementations offer higher throughput for lower clock speeds. This makes them ideal for high data rate modem implementations on FPGA's or in power limited ASIC designs. The Farrow structure offers unique advantages ideal for parallel implementation. These unique qualities allow the utilization of novel reduced complexity parallel finite-length impulse response (FIR) filters. The structures presented in this paper are suitable for implementation on application specific integrated circuits (ASIC) or field programmable gate arrays (FPGA). Results shown here are for implementation on FPGAs with varying orders of parallelization.