Fast Inverse Square Root Based Matrix Inverse for MIMO-LTE Systems

This paper addresses the designing of a low complexity and high speed matrix inversion algorithm using fast inverse square root based on QR-decomposition and systolic array architecture. Matrix operations are the most costly computational module within MIMO-LTE receivers. We have demonstrated a novel approach of matrix inverse to reduce the MIMO receiver module cost in terms of latency and complexity. The cost is reduced by implementing a 4x4 matrix inverse in Xilinx Virtex-6 FPGA by optimizing the module for speed and power by pipelining and achieving a better throughput. The results are compared with state of art techniques of CORDIC based squared givens rotation.