A Behavior Model Based on Verilog-A for 14 Bits 200MHz Current-Steering DAC

In this paper a behavioral based on Verilog-A for segmented current-steering DAC is presented. Much attention was paid to the main circuits such as bandgap reference, current cells, switch array and other relative digital circuits. In this model, non-ideal factors including mismatch of current source transistors and switch glitch are considered, and it aims to model the DAC as accurate as possible. At last the simulation data is analyzed by 8192 points FFT.