Performance aware partitioning for 3D-SOCs

Through silicon vias (TSVs) have a significant impact on the area and timing performance of a 3D-SOC. Performance aware design partitioning is required to reduce delay by placing gates on critical paths close to each other on the same or adjacent dies in the 3D-SOC. Also, pre-bond test of dies in the 3D-SOC is required to insure correct functionality of the dies before bonding. Additional design for test (DFT) logic for pre-bond test also depends on the design partitions used. In this work we propose a hypergraph based multi-objective netlist partitioning scheme to improve timing performance of 3D-SOC while keeping additional DFT cost low. Accurate interconnect estimation models are incorporated during partitioning to reduce delay and interconnect length variations across dies. Results on ISCAS89 and ITC99 benchmark circuits demonstrate the improved timing performance and reduced DFT cost using the proposed approach.