Simulation and performance evaluation of a Network-on-Chip architecture based on SystemC

The Network-on-Chip (NoC) paradigm has been recently known as a competitive on-chip communication solution for large complex systems such as multi-core and/or many-core systems thanks to its advantages. However, one of the main challenging issues for NoC designers is that the network performance should be rapidly and early pre-proved for target applications. In this paper, we present a NoC simulation and evaluation platform allowing designers to simulate and evaluate the NoC performance with different network configuration parameters. The proposed platform has been implemented in SystemC to be easily modified in order to adapt different simulation strategies and save the simulation time. With this platform, designers can deal with: (i) configuring the network topology, flow control mechanism and routing algorithm; (ii) configuring various regular and application specific traffic patterns; and (iii) simulating and analyzing the network performance with the assigned traffic patterns in terms of latency and throughput. Obtained results with a 4 × 4 2D-mesh NoC architecture will be presented and discussed in this paper to demonstrate the proposed platform.