A new circuit technique for improving transient load regulation in low-voltage CMOS LDOs

The paper presents a new circuit technique intended to improve the transient load regulation in dual-OTA CMOS LDOs, especially for low input and output voltages. The duration of overshoot that appears during fast transient load regulation is made quite small, improving the recovery of the output voltage when the output current is swept from maximum to minimum within 100ns. The presented technique is simple and needs a small number of additional components. The additional bias current is only few μA.