Design of Sample-and-Hold Circuit for a Reconfigurable ADC

In this paper, a sample-and-hold circuit for a reconfigurable ADC is presented. This design is based on TSMC 0.18μm process. Flip-around architecture is employed to implement overall circuit which may contribute to low noise and fast settling with consuming lower power. To achieve high linearity, improved bootstrapped switches are introduced in this design. A fully differential folded-cascode OTA with gain-boosting technique is utilized to obtain high gain and decrease settling time. Post-simulation results show that the OTA performs well and the whole S/H circuit achieves 65.2 dB SNDR at 60MHz clock frequency, which means that the ENOB reaches 10. The total current consumed is 3 mA.