Architectural comparison between VLIW and Vector processors

Emerging standards for wireless communication and multimedia involve complex digital signal processing (DSP) algorithms that require support for both typical DSP kernels and control-oriented tasks. Modern DSP processor architecture must meet the changing needs of DSP applications that target these very demanding standards. This paper considers the efficiency of selected DSP architectures and how they process the LTE software framework used in wireless communication. Three architectural approaches are compared - VLIW, Vector, and Hybrid approach - in terms of their performance, area, and power consumption. Performance analysis is based on a Performance Accurate Simulator (PAC) executing optimized code for each of the architectures. Area and power consumption estimates are based on a synthesis of an existing DSP processor employing a dedicated power simulator. The VLIW approach outperforms the other two architectures. However, results show that the Hybrid approach, which combines both VLIW and Vector processors, is the most efficient architecture in terms of performance-to-power ratio.