Design and Implementation of 7-bit Pipeline Analog to Digital Converter

Power dissipation of analog and mixed-signal circuits has emerged as a critical design constraint in today's VLSI systems. This paper presents a multilevel design optimization approach for reducing the power dissipation of a pipelined analog-to-digital converter. This paper describes a 7-b 75-Msample/s analog-to-digital converter fabricated in a 0.18-um CMOS technology. The converter uses pipelined eight-stage architecture with fully differential analog circuits with a full-scale sinusoidal input at 10 MHz. It dissipates 151mW.