Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-transistor architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved by its cell structure employing pseudo-spin-MOSFETs (PS-MOSFETs) that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized lowest BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and systems-on-chip (SoCs) using nonvolatile hierarchical-memory systems that are configured with NV-DFFs and nonvolatile static random access memories (NV-SRAMs).