A general purpose cell sequencer/scheduler for ATM switches

Groups of cells, such as cells belonging to different priority levels, that are all placed in one queue, can be identified by using labels or tags to distinguish them from each other. We describe a buffering device called a sequencer, which can distinguish logical queues within the same physical queue, and at the same time can successfully schedule the service among these logical queues. Scheduling the service among cells, VCs, or groups of cells in ATM switches is necessary to provide guaranteed QoS for each connection which is a major goal of ATM networks. The proposed sequencer is quite flexible and can realize different scheduling algorithms in different levels, including per VC scheduling. The sequencer can operate in real time and at very high speeds. It has a simple and modular architecture and can be implemented in a single chip. The site of the buffer can be increased simply by cascading several sequencers. The sequencer can be used as a traffic shaper, input buffer, output buffer, or a queue controller of RAM-based switches.