Accelerating NoC-Based MPI Primitives via Communication Architecture Customization

Current NoCs are always designed without the consideration of programming models, bringing about a great challenge for exploiting parallelism. In this paper, we present a NoC design that take into account the well-known parallel programming model, message passing interface (MPI), to boost applications by exploiting all hardware features available in the NoC-based multicore architectures. Conventional MPI functions are normally implemented in software due to their enormity and complexity, resulting in large communication latencies. We propose a new hardware implementation of basic MPI primitives. The premise is that all other MPI functions can be efficiently built upon these three MPI primitives. Our design includes two important hardware features: the customized NoC design incorporating virtual buses (VB) into NoCs and the optimized MPI unit (MU) efficiently executing MPI-related transactions. Extensive experimental results have demonstrated that the proposed designs effectively boost the performance of MPI primitives.