A 60 GHz dual-mode power amplifier with 17.4 dBm output power and 29.3% PAE in 40-nm CMOS

A 60 GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. The PA consists of two unit PAs with a transformer-based power combiner at the output. To reduce the power consumption and hence extend battery life time, one unit PA is tuned off in low-power mode. A switch is employed to short the output of this off-state unit PA and thus improves the back-off efficiency. The PA achieves a saturated output power (P
_SAT
) of 17.4 dBm with 29.3% PAE in high-power mode and a P
_SAT
of 12.6 dBm with 19.6% PAE in low-power mode. The PA with the power combiner only consumes an active area of 0.074 mm
²
. The reliability measurements are also performed and the PA has an estimated lifetime of 80613 hours.